This invention relates generally to integrated circuits and more particularly to circuitry for adjusting or trimming the offset voltage of a differential amplifier of an integrated circuit.
As is known, an integrated circuit (IC) such as an operational amplifier (op amp), comparator or analog-to digital (A/D) or digital-to-analog (D/A) converter commonly includes a differential amplifier as the amplifying stage thereof. The differential amplifier typically comprises a pair of emitter-coupled, bipolar transistors having the base electrodes thereof fed by a pair of input signals. The coupled emitters are coupled to a constant current source. The collector electrodes of the pair of transistors are each coupled to a supply voltage through a predetermined resistance, with the differential output of the transistor pair being taken between such collector electrodes. Due to fabrication-induced mismatches between such pair of transistors, the differential amplifier requires a finite offset voltage to set the differential output voltage of the transistor pair to zero volts. As is known, such offset voltage is a function of the value of the collector resistances of the differential transistor pair; that is, adjusting the value of such resistances will vary the offset voltage.
Conventionally, offset voltage adjustment is performed while the integrated circuit is at the wafer level, that is, before an individual integrated circuit chip (commonly termed a "die") has been scribed and separated from an integrated circuit wafer (typically comprising an array of dice) and packaged in an integrated circuit package. Typically, the total collector resistance of each one of the differential pair of transistors of the integrated circuit is implemented as a plurality of discrete resistors serially coupled between the supply voltage and collector electrode, and a selected one, or ones, of such discrete resistors is shunted with a corresponding one, or ones, of zener diodes. That is, individual zener diodes are connected in parallel across selected individual collector resistors. Pads are provided on each individual integrated circuit chip or die at the anode and cathode electrodes of each zener diode. A large reverse-bias voltage is applied individually across a selected one, or ones, of the zener diodes, thereby inducing a sufficiently large reverse current therethrough to permanently short-circuit such selected one, or ones, of the zener diodes. The discrete resistors shunted by the short-circuited zener diodes thus are electrically bypassed, thereby incrementally reducing the collector resistance of the one of the pair of transistors coupled thereto and trimming the offset voltage of the differential pair of transistors. Typically, such offset voltage is trimmed in this manner to reduce the magnitude of the offset voltage to as close as possible to zero volts. That is, such offset voltage is "nulled".
While such arrangement for adjusting the differential amplifier offset voltage of an integrated circuit is satisfactory in some applications, it is noted that after an individual integrated circuit chip or die is separated from the wafer, such chip typically is assembled into an integrated circuit package, such as a dual-in-line package (DIP), flatpack or TO-5 can, having a predetermined and limited number of package leads or pins. Thus, such an integrated circuit package typically does not provide leads or pins coupled to the chip-level pads of the offset-voltage-trimming zener diodes. That is, the pads for the offset-voltage-trimming zener diodes are not accessible through the leads of the package containing the integrated circuit differential amplifier. Thus, the above-described offset voltage adjustment is performed only at the integrated circuit wafer level, that is, before an individual integrated circuit chip or die is assembled into an integrated circuit package. Thus, compensation is not provided for changes in the offset voltage of the differential amplifier which are typically introduced during the separation of the integrated circuit wafer into dice (i.e., individual die), the assembly of an individual integrated circuit die into an IC package and the burn-in phase of the packaged integrated circuit. Thus, the offset voltage of the finally-packaged integrated circuit often has shifted by tens of microvolts from the offset voltage null obtained at the integrated circuit wafer level.